The present invention relates to a high-speed digital accumulator with wide dynamic range. More particularly, the invention relates to a high-speed digital accumulator with wide dynamic range which uses a twos-complement digital adder.
It is known that digital accumulators consist of an adder which receives an input and the value of the accumulator itself in the preceding time period. In practice, the transfer function of said digital accumulators in Z-transforms is as follows:   Y  =            z              z        -        1              ·    X  
FIG. 1 illustrates a digital accumulator executed according to the prior art.
As shown in FIG. 1, the accumulator thus comprises a digital adder 1, the input whereof receives an addend X which is m bits long and also receives the value of the accumulator during the preceding clock period; said value has a length of n bits, since the adder is an n-bit adder. In this case, the output datum Y has a length of n bits.
The reference numeral 2 designates an accumulation register for the result of the adder 1.
In this structure it is assumed that n is much larger than m.
The above-described structure has the drawback that it is inherently slow, since the sum performed by the adder 1 must be completed in a time which is short enough to satisfy the following relation:
Tsum(n)+Tsetup less than Tclock
The pass time of the n-bit adder 1 added to the setup time of the bank of the register 2 must be shorter than the clock time with which the structure is supplied.
Accordingly, it is sometimes difficult to satisfy the above relation, especially in high-speed applications, where it is not possible to use simple ripple-carry adders and therefore structures of the look-ahead or carry select type are used, always with the ultimate goal of satisfying the above equation.
The aim of an embodiment of the present invention is therefore to provide a high-speed digital accumulator with wide dynamic range which has a very large number of significant digits with respect to the operating frequency.
Within the scope of this aim, an advantage of an embodiment of the present invention is to provide a high-speed digital accumulator with wide dynamic range which allows to perform the operation of a digital accumulator in at least two clock cycles by means of a pipeline.
Another advantage of an embodiment of the present invention is to provide a high-speed digital accumulator with wide dynamic range which uses a high-speed, reduced-area twos-complement digital adder.
Another advantage of an embodiment of the present invention is to provide a high-speed digital accumulator with wide dynamic range which is highly reliable, relatively easy to manufacture and at competitive costs.
This aim, these advantages and others which will become apparent hereinafter are achieved by an embodiment of a high-speed digital accumulator with wide dynamic range, characterized in that it comprises a first adder stage, in which an input addend is added to a value of a least significant part of an accumulator at the preceding clock period, and at least one second stage, which comprises incrementer/decrementer means suitable to perform an increment, decrement or identity operation on a most significant part of said accumulator, said incrementer/decrementer means further comprising logic means suitable to trigger an increment, a decrement or an identity of said most significant part on the basis of a decision made on results obtained at the preceding clock period.
Further characteristics and advantages of the invention will become apparent from the description of embodiments of the digital accumulator according to the invention, illustrated only by way of non-limitative example in the accompanying drawings.